ASIC RTL Design Engineer

发布时间:2019年01月29日 11:01    发布者:KT咨询
快乐牛牛在线玩官网: RTL , Design

NO.487-【猎头职位:深圳需要五位 ASIC RTL Design Engineer】联系人:Raymond-Chen,邮箱:hr@kthr.com,微信也可查询职位了!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加,欢迎大家关注!

Job Description:

Ø  Design RTL for our CPU-centric MachineLearning ASIC chip

Ø  Optimize timing and power consumption

Ø  Support functionality debug in simulation andemulation

Ø  Write timing/power constraint for the design

Job Requirement:

MUST

Ø  MS or PhD degree in Electrical Engineering,Computer Science, Physics, Mathematics or equivalent disciplines.

Ø  MS with > 2 years of industrialexperience; more experiences and capability will correspond to higher joblevels.

Ø  Excellent RTL design skills with SystemVerilog.

Ø  Good scripting skills with Python/Perl/Tcl.

Ø  Solid understanding of low power optimization.

Ø  Proficient communication in English - bothorally and in writing form.

Ø  Self-driven, result-oriented; able tomulti-task and determine priorities.

Ø  A proven fast learner and a team player.

PREFERRED

Ø  Knowledge and experience with RISC-V ISA ishighly desired.

Ø  Knowledge about CPU architecture and memoryhierarchy.

Ø  Experience of working with foreign coworkersand remote teams is a plus.

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